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? 2003-2013 microchip technology inc. ds21805b-page 1 mcp3021 features ? 10-bit resolution ? 1 lsb dnl, 1 lsb inl max. ? 250 a max conversion current ? 5 na typical standby current, 1 a max. ?i 2 c? compatible serial interface -100khz i 2 c standard mode -400khz i 2 c fast mode ? up to 8 devices on single 2-wire bus ? 22.3 ksps in i 2 c fast mode ? single-ended analog input channel ? on-chip sample and hold ? on-chip conversion clock ? single supply specified operation: 2.7v to 5.5v ? temperature range: - extended: -40c to +125c ?small sot-23 package applications ? data logging ? multi-zone monitoring ? hand held portable applications ? battery powered test equipment ? remote or isolated data acquisition package type description the microchip technology inc. mcp3021 is a succes- sive approximation a/d converter (adc) with 10-bit resolution. available in the sot-23 package, this device provides one single-ended input with very low power consumption. based on an advanced cmos technology, the mcp3021 provides a low maximum conversion current and standby current of 250 a and 1 a, respectively. low current consumption, com- bined with the small sot-23 package, make this device ideal for battery-powered and remote data acquisition applications. communication to the mcp3021 is performed using a 2-wire i 2 c compatible interface. standard (100 khz) and fast (400 khz) i 2 c modes are available with the device. an on-chip conversion clock enables indepen- dent timing for the i 2 c and conversion clocks. the device is also addressable, allowing up to eight devices on a single 2-wire bus. the mcp3021 runs on a single supply voltage that operates over a broad range of 2.7v to 5.5v. this device also provides excellent linearity of 1 lsb differ- ential non-linearity (dnl) and 1 lsb integral non- linearity (inl), maximum. functional block diagram 5-pin sot-23a scl ain mcp3021 1 2 3 5 sda v ss v dd 4 comparator 10-bit sar dac ain v ss v dd scl sda clock control logic ? + sample and hold i 2 c? interface low power 10-bit a/d converter with i 2 c? interface
mcp3021 ds21805b-page 2 ? 2003-2013 microchip technology inc. 1.0 electrical characteristics absolute maximum ratings ? v dd ...................................................................................7.0v analog input pin w.r.t. v ss .......... ............. -0.6v to v dd +0.6v sda and scl pins w.r.t. v ss ........... .........-0.6v to v dd +1.0v storage temperature .....................................-65c to +150c ambient temp. with power applied ................-65c to +125c maximum junction temperature .......... .........................150c esd protection on all pins (hbm) ................................. ? 4kv ? stresses above those listed under ?maximum ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational list- ings of this specification is not implied. exposure to maximum rating conditions for extended periods may affect device reli- ability. pin function table name function v dd +2.7v to 5.5v power supply v ss ground ain analog input sda serial data in/out scl serial clock in dc electrical specifications electrical characteristics: unless otherwise noted, all parameters apply at v dd = 5.0v, v ss = gnd, r pu = 2 k ? t a = -40c to +85c, i 2 c fast mode timing: f scl = 400 khz ( note 3 ). parameters sym min typ max units conditions dc accuracy resolution 10 bits integral nonlinearity inl ? 0.25 1 lsb differential nonlinearity dnl ? 0.25 1 lsb no missing codes offset error ? 0.75 3 lsb gain error ? -1 3 lsb dynamic performance total harmonic distortion thd ? -70 ? db v in = 0.1v to 4.9v @ 1 khz signal to noise and distortion sinad ? 60 ? db v in = 0.1v to 4.9v @ 1 khz spurious free dynamic range sfdr ? 74 ? db v in = 0.1v to 4.9v @ 1 khz analog input input voltage range v ss -0.3 ? v dd +0.3 v 2.7v ? v dd ? 5.5v leakage current -1 ? +1 a sda/scl (open-drain output) data coding format straight binary high-level input voltage v ih 0.7 v dd ??v low-level input voltage v il ??0.3 v dd v low-level output voltage v ol ??0.4vi ol = 3 ma, r pu = 1.53 k ? hysteresis of schmitt trigger inputs v hyst ? 0.05v dd ?vf scl = 400 khz only note 1: sample time is the time between conversions after the address byte has been sent to the converter. refer to figure 5-6. 2: this parameter is periodically sampled and not 100% tested. 3: r pu = pull-up resistor on sda and scl. 4: sda and scl = v ss to v dd at 400 khz. 5: t acq and t conv are dependent on internal oscillator timing. see figure 5-5 and figure 5-6 for relation to scl.
? 2003-2013 microchip technology inc. ds21805b-page 3 mcp3021 temperature specifications input leakage current i li -1 ? +1 a v in = v ss to v dd output leakage current i lo -1 ? +1 a v out = v ss to v dd pin capacitance (all inputs/outputs) c in , c out ?? 10pft amb = 25c, f = 1 mhz; ( note 2 ) bus capacitance c b ? ? 400 pf sda drive low, 0.4v power requirements operating voltage v dd 2.7 ? 5.5 v conversion current i dd ?175250a standby current i dds ?0.005 1 asda, scl = v dd active bus current i dda ? ? 120 a note 4 conversion rate conversion time t conv ?8.96 ? s note 5 analog input acquisition time t acq ?1.12 ? s note 5 sample rate f samp ? ? 22.3 ksps f scl = 400 khz ( note 1 ) electrical characteristics: all parameters apply across the operating voltage range. parameters symbol min typ max units conditions temperature ranges extended temperature range t a -40 ? +125 c operating temperature range t a -40 ? +125 c storage temperature range t a -65 ? +150 c thermal package resistances thermal resistance, 5l-sot23a ? ja ? 256 ? c/w dc electrical specifications (continued) electrical characteristics: unless otherwise noted, all parameters apply at v dd = 5.0v, v ss = gnd, r pu = 2 k ? t a = -40c to +85c, i 2 c fast mode timing: f scl = 400 khz ( note 3 ). parameters sym min typ max units conditions note 1: sample time is the time between conversions after the address byte has been sent to the converter. refer to figure 5-6. 2: this parameter is periodically sampled and not 100% tested. 3: r pu = pull-up resistor on sda and scl. 4: sda and scl = v ss to v dd at 400 khz. 5: t acq and t conv are dependent on internal oscillator timing. see figure 5-5 and figure 5-6 for relation to scl.
mcp3021 ds21805b-page 4 ? 2003-2013 microchip technology inc. timing specifications figure 1-1: standard and fast mode bus timing data. electrical characteristics: all parameters apply at v dd = 2.7v - 5.5v, v ss = gnd, t a = -40c to +85c. parameters sym min typ max units conditions i 2 c standard mode clock frequency f scl 0?100khz clock high time t high 4000 ? ? ns clock low time t low 4700 ? ? ns sda and scl rise time t r ? ? 1000 ns from v il to v ih ( note 1 ) sda and scl fall time t f ??300nsfrom v il to v ih ( note 1 ) start condition hold time t hd:sta 4000 ? ? ns start condition setup time t su:sta 4700 ? ? ns data input setup time t su:dat 250 ? ? ns stop condition setup time t su:sto 4000 ? ? ns stop condition hold time t hd:std 4000 ? ? ns output valid from clock t aa ? ? 3500 ns bus free time t buf 4700 ? ? ns note 2 input filter spike suppression t sp ? ? 50 ns sda and scl pins (note 1) i 2 c fast mode clock frequency f scl 0?400khz clock high time t high 600 ? ? ns clock low time t low 1300 ? ? ns sda and scl rise time t r 20 + 0.1c b ? 300 ns from v il to v ih (note 1) sda and scl fall time t f 20 + 0.1c b ? 300 ns from v il to v ih (note 1) start condition hold time t hd:sta 600 ? ? ns start condition setup time t su:sta 600 ? ? ns data input hold time t hd:dat 0?0.9ms data input setup time t su:dat 100 ? ? ns stop condition setup time t su:sto 600 ? ? ns stop condition hold time t hd:std 600 ? ? ns output valid from clock t aa ??900ns bus free time t buf 1300 ? ? ns note 2 input filter spike suppression t sp ? ? 50 ns sda and scl pins (note 1) note 1: this parameter is periodically sampled and not 100% tested. 2: time the bus must be free before a new transmission can start. t f t high v hys t r t su:sta t sp t hd:sta t low t hd:dat t su:dat t su:sto t buf t aa scl sda in sda out
? 2003-2013 microchip technology inc. ds21805b-page 5 mcp3021 2.0 typical performance curves note: unless otherwise indicated, v dd = 5v, v ss = 0v, i 2 c fast mode timing (scl = 400 khz), continuous conversion mode (f samp = 22.3 ksps), t a = +25c. figure 2-1: inl vs. clock rate. figure 2-2: inl vs. v dd - i 2 c standard mode (f scl = 100 khz). figure 2-3: inl vs. code (representative part). figure 2-4: inl vs. clock rate (v dd =2.7v). figure 2-5: inl vs. v dd - i 2 c fast mode (f scl = 400 khz). figure 2-6: inl vs. code (representative part, v dd = 2.7v). note: the graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. the performance characteristics listed herein are not tested or guaranteed. in some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore outside the warranted range. -1 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1 0 100 200 300 400 i 2 c bus rate (khz) inl (lsb) positive inl negative inl 0.25 0.20 0.15 0.10 0.005 -0.005 -0.10 -0.15 -0.20 -0.25 -1 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1 2.533.544.555.5 v dd (v) inl (lsb) positive inl negative inl 0.25 0.20 0.15 0.10 0.005 -0.005 -0.10 -0.15 -0.20 -0.25 -0.5 -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 0.5 0 256 512 768 1024 digital code inl (lsb) -1 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1 0 100 200 300 400 i 2 c bus rate (khz) inl (lsb) positive inl negative inl 0.25 0.20 0.15 0.10 0.005 -0.005 -0.10 -0.15 -0.20 -0.25 -1 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1 2.533.544.555.5 v dd (v) inl (lsb) positive inl negative inl 0.25 0.20 0.15 0.10 0.005 -0.005 -0.10 -0.15 -0.20 -0.25 -0.5 -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 0.5 0 256 512 768 1024 digital code inl (lsb)
mcp3021 ds21805b-page 6 ? 2003-2013 microchip technology inc. note: unless otherwise indicated, v dd = 5v, v ss = 0v, i 2 c fast mode timing (scl = 400 khz), continuous conversion mode (f samp = 22.3 ksps), t a = +25c. figure 2-7: inl vs. temperature. figure 2-8: dnl vs. clock rate. figure 2-9: dnl vs. v dd - i 2 c standard mode (f scl = 100 khz). figure 2-10: inl vs. temperature (v dd =2.7v). figure 2-11: dnl vs. clock rate (v dd =2.7v). figure 2-12: dnl vs. v dd - i 2 c fast mode (f scl = 400 khz). -1 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1 -50 -25 0 25 50 75 100 125 temperature (c) inl (lsb) positive inl negative inl 0.25 0.20 0.15 0.10 0.005 -0.005 -0.10 -0.15 -0.20 -0.25 -1 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1 0 100 200 300 400 i 2 c bus rate (khz) dnl (lsb) positive dnl negative dnl 0.25 0.20 0.15 0.10 0.005 -0.005 -0.10 -0.15 -0.20 -0.25 -1 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1 2.5 3 3.5 4 4.5 5 5.5 v dd (v) dnl (lsb) positive dnl negative dnl 0.25 0.20 0.15 0.10 0.005 -0.005 -0.10 -0.15 -0.20 -0.25 -1 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1 -50-25 0 255075100125 temperature (c) inl (lsb) negative inl positive inl 0.25 0.20 0.15 0.10 0.005 -0.005 -0.10 -0.15 -0.20 -0.25 -1 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1 0 100 200 300 400 i 2 c bus rate (khz) dnl (lsb) negative dnl positive dnl 0.25 0.20 0.15 0.10 0.005 -0.005 -0.10 -0.15 -0.20 -0.25 -1 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1 2.533.544.555.5 v dd (v) dnl (lsb) positive dnl negative dnl 0.25 0.20 0.15 0.10 0.005 -0.005 -0.10 -0.15 -0.20 -0.25
? 2003-2013 microchip technology inc. ds21805b-page 7 mcp3021 note: unless otherwise indicated, v dd = 5v, v ss = 0v, i 2 c fast mode timing (scl = 400 khz), continuous conversion mode (f samp = 22.3 ksps), t a = +25c. figure 2-13: dnl vs. code (representative part). figure 2-14: dnl vs. temperature. figure 2-15: gain error vs. v dd . figure 2-16: dnl vs. code (representative part, v dd = 2.7v). figure 2-17: dnl vs. temperature (v dd =2.7v). figure 2-18: offset error vs. v dd . -0.5 -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 0.5 0 256 512 768 1024 digital code dnl (lsb) -1 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1 -50 -25 0 25 50 75 100 125 temperature (c) dnl (lsb) negative dnl positive dnl 0.25 0.20 0.15 0.10 0.005 -0.005 -0.10 -0.15 -0.20 -0.25 -1 -0.9 -0.8 -0.7 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0 2.533.544.555.5 v dd (v) gain error (lsb) fast mode (f scl =100 khz) standard mode (f scl =400 khz) 0 -0.025 -0.05 -0.075 -0.1 -0.15 -0.175 -0.2 -0.225 -0.25 -0.125 -0.5 -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 0.5 0 256 512 768 1024 digital code dnl (lsb) -1 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1 -50 -25 0 25 50 75 100 125 temperature (c) dnl (lsb) positive dnl negative dnl 0.25 0.20 0.15 0.10 0.005 -0.005 -0.10 -0.15 -0.20 -0.25 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 2.533.544.555.5 v dd (v) offset error (lsb) f scl = 100 khz & 400 khz 0.25 0.225 0.2 0.175 0.15 0.1 0.075 0.05 0.025 0 0.125
mcp3021 ds21805b-page 8 ? 2003-2013 microchip technology inc. note: unless otherwise indicated, v dd = 5v, v ss = 0v, i 2 c fast mode timing (scl = 400 khz), continuous conversion mode (f samp = 22.3 ksps), t a = +25c. figure 2-19: gain error vs. temperature. figure 2-20: snr vs. input frequency. figure 2-21: thd vs. input frequency. figure 2-22: offset error vs. temperature. figure 2-23: sinad vs. input frequency. figure 2-24: sinad vs. input signal level. -1.5 -1 -0.5 0 0.5 1 1.5 -50 -25 0 25 50 75 100 125 temperature (c) gain error (lsb) v dd = 5v v dd = 2.7v 0.375 0.250 0.125 -0.125 -0.250 -0.375 12 24 36 48 60 72 84 96 110 input frequency (khz) snr (db) v dd = 5v v dd = 2.7v y 84 72 60 48 36 24 12 0 -96 -84 -72 -60 -48 -36 -24 -12 110 input frequency (khz) thd (db) v dd = 2.7v v dd = 5v 0 -12 -24 -36 -48 -60 -72 -84 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 -50 -25 0 25 50 75 100 125 temperature (c) offset error (lsb) v dd = 5v v dd = 2.7v 0.50 0.45 0.40 0.35 0.30 0.25 0.15 0.10 0.05 0 0.20 12 24 36 48 60 72 84 96 110 input frequency (khz) sinad (db) v dd = 5v v dd = 2.7v 84 72 60 48 36 24 12 0 12 24 36 48 60 72 84 96 -40 -30 -20 -10 0 input signal level (db) sinad (db) v dd = 5v v dd = 2.7v 84 72 60 48 36 24 12 0
? 2003-2013 microchip technology inc. ds21805b-page 9 mcp3021 note: unless otherwise indicated, v dd = 5v, v ss = 0v, i 2 c fast mode timing (scl = 400 khz), continuous conversion mode (f samp = 22.3 ksps), t a = +25c. figure 2-25: enob vs. v dd . figure 2-26: sfdr vs. input frequency. figure 2-27: spectrum using i 2 c fast mode (representative part, 1 khz input frequency). figure 2-28: enob vs. input frequency. figure 2-29: spectrum using i 2 c standard mode (representative part, 1 khz input frequency). figure 2-30: i dd (conversion) vs. v dd . 11.5 11.55 11.6 11.65 11.7 11.75 11.8 11.85 11.9 11.95 12 2.533.544.555.5 v dd (v) enob (rms) 10 9.95 9.90 9.85 9.80 9.75 9.70 9.65 9.60 9.55 9.50 12 24 36 48 60 72 84 96 110 input frequency (khz) sfdr (db) v dd = 2.7v v dd = 5 v 84 72 60 48 36 24 12 0 -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 10 0 2000 4000 6000 8000 10000 frequency (hz) amplitude (db) 9 9.5 10 10.5 11 11.5 12 110 input frequency (khz) enob (rms) v dd = 2.7v v dd = 5v 10 9.5 9.0 8.5 8.0 7.7 7.0 -130 -110 -90 -70 -50 -30 -10 10 0 500 1000 1500 2000 2500 frequency (hz) amplitude (db) 0 50 100 150 200 250 2.5 3 3.5 4 4.5 5 5.5 v dd (v) i dd (a)
mcp3021 ds21805b-page 10 ? 2003-2013 microchip technology inc. note: unless otherwise indicated, v dd = 5v, v ss = 0v, i 2 c fast mode timing (scl = 400 khz), continuous conversion mode (f samp = 22.3 ksps), t a = +25c. figure 2-31: i dd (conversion) vs. clock rate. figure 2-32: i dd (conversion) vs. temperature. figure 2-33: i dda (active bus) vs. v dd . figure 2-34: i dda (active bus) vs. clock rate. figure 2-35: i dda (active bus) vs. temperature. figure 2-36: i dds (standby) vs. v dd . 0 20 40 60 80 100 120 140 160 180 200 0 100 200 300 400 i 2 c clock rate (khz) i dd (a) v dd = 5v v dd = 2.7v 0 50 100 150 200 250 -50 -25 0 25 50 75 100 125 temperature (c) i dd (a) v dd = 5v v dd = 2.7v 0 10 20 30 40 50 60 70 80 90 100 2.5 3 3.5 4 4.5 5 5.5 v dd (v) i dda (a) 0 10 20 30 40 50 60 70 80 90 100 0 100 200 300 400 i 2 c clock rate (khz) i dda (a) v dd = 5v v dd = 2.7v 0 10 20 30 40 50 60 70 80 90 100 -50 -25 0 25 50 75 100 125 temperature (c) i dda (a) v dd = 5v v dd = 2.7v 0 10 20 30 40 50 60 2.5 3 3.5 4 4.5 5 5.5 v dd (v) i dds (pa)
? 2003-2013 microchip technology inc. ds21805b-page 11 mcp3021 note: unless otherwise indicated, v dd = 5v, v ss = 0v, i 2 c fast mode timing (scl = 400 khz), continuous conversion mode (f samp = 22.3 ksps), t a = +25c. figure 2-37: i dds (standby) vs. temperature. figure 2-38: analog input leakage vs. temperature. 2.1 test circuit figure 2-39: typical test configuration. 0.0001 0.001 0.01 0.1 1 10 100 1000 -50 -25 0 25 50 75 100 125 temperature (c) i dds (na) 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 -50 -25 0 25 50 75 100 125 temperature (c) analog input l eakage (na) 0.1 f ain mcp3021 v dd = 5v v cm = 2.5v v in v dd v ss 10 f sda scl 2k ? 2k ?
mcp3021 ds21805b-page 12 ? 2003-2013 microchip technology inc. 3.0 pin functions table 3-1: pin function table 3.1 v dd and v ss the v dd pin, with respect to v ss , provides power to the device, as well as a voltage reference for the conver- sion process. refer to section 6.4, ?device power and layout considerations?, for tips on power and grounding. 3.2 analog input (ain) ain is the input pin to the sample and hold circuitry of the successive approximation register (sar) con- verter. care should be taken in driving this pin. refer to section 6.1, ?driving the analog input?. for proper con- versions, the voltage on this pin can vary from v ss to v dd . 3.3 serial data (sda) this is a bidirectional pin used to transfer addresses and data into and out of the device. it is an open-drain terminal, therefore, the sda bus requires a pull-up resistor to v dd (typically 10 k ? for 100 khz and 2 k ? for 400 khz scl clock speeds (refer to section 6.2, ?connecting to the i 2 c bus?). for normal data transfer, sda is allowed to change only during scl low. changes during scl high are reserved for indicating the start and stop conditions (refer to section 5.1, ?i 2 c bus characteristics?). 3.4 serial clock (scl) scl is an input pin used to synchronize the data trans- fer to and from the device on the sda pin and is an open-drain terminal. therefore, the scl bus requires a pull-up resistor to v dd (typically, 10 k ? for 100 khz and 2k ? for 400 khz scl clock speeds. refer to section 6.2, ?connecting to the i 2 c bus?). for normal data transfer, sda is allowed to change only during scl low. changes during scl high are reserved for indicating the start and stop conditions (refer to section 6.1, ?driving the analog input?). name function v dd +2.7v to 5.5v power supply v ss ground ain analog input sda serial data in/out scl serial clock in
? 2003-2013 microchip technology inc. ds21805b-page 13 mcp3021 4.0 device operation the mcp3021 employs a classic sar architecture. this architecture uses an internal sample and hold capacitor to store the analog input while the conversion is taking place. at the end of the acquisition time, the input switch of the converter opens and the device uses the collected charge on the internal sample and hold capacitor to produce a serial 10-bit digital output code. the acquisition time and conversion is self-timed using an internal clock. after each conversion, the results are stored in a 10-bit register that can be read at any time. communication with the device is accomplished with a 2-wire i 2 c interface. maximum sample rates of 22.3 ksps are possible with the mcp3021 in a continu- ous conversion mode and an scl clock rate of 400 khz. 4.1 digital output code the digital output code produced by the mcp3021 is a function of the input signal and power supply voltage (v dd ). as the v dd level is reduced, the lsb size is reduced accordingly. the theoretical lsb size is shown below. equation the output code of the mcp3021 is transmitted serially with msb first, the format of the code being straight binary. 4.2 conversion time (t conv ) the conversion time is the time required to obtain the digital result once the analog input is disconnected from the holding capacitor. with the mcp3021, the specified conversion time is typically 8.96 s. this time is dependent on the internal oscillator and independent of scl. 4.3 acquisition time (t acq ) the acquisition time is the amount of time the sample cap array is acquiring charge. the acquisition time is, typically, 1.12 s. this time is dependent on the internal oscillator and independent of scl. 4.4 sample rate sample rate is the inverse of the maximum amount of time that is required from the point of acquisition of the first conversion to the point of acquisition of the second conversion. the sample rate can be measured either by single or continuous conversions. a single conversion includes a start bit, address byte, two data bytes and a stop bit. this sample rate is measured from one start bit to the next start bit. for continuous conversions (requested by the master by issuing an acknowledge after a conversion), the maximum sample rate is measured from conversion to conversion, or a total of 18 clocks (two data bytes and two acknowledge bits). refer to section 5-2, ?device addressing?. figure 4-1: transfer function. lsb size v dd 1024 ----------- - = v dd = supply voltage ain 00 0000 0001 (1) 00 0000 0011 (3) 11 1111 1110 (1022) output code v dd -1.5 lsb .5 lsb 1.5 lsb v dd -2.5 lsb 2.5 lsb 00 0000 0000 (0) 00 0000 0010 (2) 11 1111 1111 (1023)
mcp3021 ds21805b-page 14 ? 2003-2013 microchip technology inc. 4.5 differential non-linearity (dnl) in the ideal adc transfer function, each code has a uni- form width. that is, the difference in analog input volt- age is constant from one code transition point to the next. dnl specifies the deviation of any code in the transfer function from an ideal code width of 1 lsb. the dnl is determined by subtracting the locations of successive code transition points after compensating for any gain and offset errors. a positive dnl implies that a code is longer than the ideal code width, while a negative dnl implies that a code is shorter than the ideal width. 4.6 integral non-linearity (inl) inl is a result of cumulative dnl errors and specifies how much the overall transfer function deviates from a linear response. the method of measurement used in the mcp3021 adc to determine inl is the ?end-point? method. 4.7 offset error offset error is defined as a deviation of the code transi- tion points that are present across all output codes. this has the effect of shifting the entire a/d transfer function. the offset error is measured by finding the dif- ference between the actual location of the first code transition and the desired location of the first transition. the ideal location of the first code transition is located at 1/2 lsb above v ss . 4.8 gain error the gain error determines the amount of deviation from the ideal slope of the adc transfer function. before the gain error is determined, the offset error is measured and subtracted from the conversion result. the gain error can then be determined by finding the location of the last code transition and comparing that location to the ideal location. the ideal location of the last code transition is 1.5 lsbs below full-scale or v dd . 4.9 conversion current (i dd ) the average amount of current over the time required to perform a 10-bit conversion. 4.10 active bus current (i dda ) the average amount of current over the time required to monitor the i 2 c bus. any current the device con- sumes while it is not being addressed is referred to as active bus current. 4.11 standby current (i dds ) the average amount of current required while no con- version is occurring and while no data is being output (i.e., scl and sda lines are quiet). 4.12 i 2 c standard mode timing i 2 c specification where the frequency of scl is 100 khz. 4.13 i 2 c fast mode timing i 2 c specification where the frequency of scl is 400 khz.
? 2003-2013 microchip technology inc. ds21805b-page 15 mcp3021 5.0 serial communications 5.1 i 2 c bus characteristics the following bus protocol has been defined: ? data transfer may be initiated only when the bus is not busy. ? during data transfer, the data line must remain stable whenever the clock line is high. changes in the data line while the clock line is high will be interpreted as a start or stop condition. accordingly, the following bus conditions have been defined (refer to figure 5-1). 5.1.1 bus not busy (a) both data and clock lines remain high. 5.1.2 start data transfer (b) a high-to-low transition of the sda line while the clock (scl) is high determines a start condition. all commands must be preceded by a start condition. 5.1.3 stop data transfer (c) a low-to-high transition of the sda line while the clock (scl) is high determines a stop condition. all operations must be ended with a stop condition. 5.1.4 data valid (d) the state of the data line represents valid data when, after a start condition, the data line is stable for the duration of the high period of the clock signal. the data on the line must be changed during the low period of the clock signal. there is one clock pulse per bit of data. each data transfer is initiated with a start condition and terminated with a stop condition. the number of data bytes transferred between the start and stop conditions is determined by the master device and is unlimited. 5.1.5 acknowledge each receiving device, when addressed, is obliged to generate an acknowledge bit after the reception of each byte. the master device must generate an extra clock pulse that is associated with this acknowledge bit. the device that acknowledges has to pull down the sda line during the acknowledge clock pulse in such a way that the sda line is stable low during the high period of the acknowledge-related clock pulse. setup and hold times must be taken into account. during reads, a master device must signal an end of data to the slave by not generating an acknowledge bit on the last byte that has been clocked out of the slave (nak). in this case, the slave (mcp3021) will release the bus to allow the master device to generate the stop con- dition. the mcp3021 supports a bidirectional 2-wire bus and data transmission protocol. the device that sends data onto the bus is the transmitter and the device receiving data is the receiver. the bus has to be controlled by a master device that generates the serial clock (scl), controls the bus access and generates the start and stop conditions, while the mcp3021 works as a slave device. both master and slave devices can operate as either transmitter or receiver, but the master device determines which mode is activated. figure 5-1: data transfer sequence on the serial bus. scl sda (a) (b) (d) (d) (a) (c) start condition address or acknowledge valid data allowed to change stop condition
mcp3021 ds21805b-page 16 ? 2003-2013 microchip technology inc. 5.2 device addressing the address byte is the first byte received following the start condition from the master device. the first part of the control byte consists of a 4-bit device code, which is set to 1001 for the mcp3021. the device code is fol- lowed by three address bits: a2, a1 and a0. the default address bits are 101 (contact the microchip factory for additional address bit options).the address bits allow up to eight mcp3021 devices on the same bus and are used to determine which device is accessed. the eighth bit of the slave address determines if the master device wants to read conversion data or write to the mcp3021. when set to a ? 1 ?, a read operation is selected. when set to a ? 0 ?, a write operation is selected. there are no writable registers on the mcp3021, therefore, this bit must be set to a ? 1 ? to initiate a conversion. the mcp3021 is a slave device that is compatible with the 2-wire i 2 c serial interface protocol. a hardware connection diagram is shown in figure 6-2. communi- cation is initiated by the microcontroller (master device), which sends a start bit followed by the address byte. on completion of the conversion(s) performed by the mcp3021, the microcontroller must send a stop bit to stop the communication. the last bit in the device address byte is the r/w bit. when this bit is a logic ? 1 ?, a conversion will be exe- cuted. setting this bit to logic ? 0 ? will also result in an ?acknowledge? (ack) from the mcp3021, with the device then releasing the bus. this can be used for device polling (refer to section 6.3, ?device polling?). figure 5-2: device addressing. 5.3 executing a conversion this section will describe the details of communicating with the mcp3021 device. initiating the sample and hold acquisition, reading the conversion data and executing multiple conversions will be discussed. 5.3.1 initiating the sample and hold the acquisition and conversion of the input signal begins with the falling edge of the r/w bit of the address byte. at this point, the internal clock initiates the sample, hold and conversion cycle, all of which are internal to the adc. figure 5-3: initiating the conversion, address byte. figure 5-4: initiating the conversion, continuous conversions. start read/write slave address r/w a 1 0 0 1 10 1 address bits 1 1 contact microchip for additional address bits. device code 123456789 scl sda 1 0 0 1 a2 a1 a0 r/w ack start bit address byte address bits device bits t acq + t conv is initiated here scl sda d1 d0 x ack lower data byte (n) t acq + t conv is initiated here d4 d3 d2 x d5 ack d6 17 18 19 20 21 22 23 24 25 26
? 2003-2013 microchip technology inc. ds21805b-page 17 mcp3021 the input signal will initially be sampled with the first falling edge of the clock following the transmission of a logic-high r/w bit. additionally, with the rising edge of the scl, the adc will transmit an acknowledge bit (ack = 0 ). the master must release the data bus dur- ing this clock pulse to allow the mcp3021 to pull the line low (refer to figure 5-3). for consecutive samples, sampling begins on the last bit of the lower data byte. refer to figure 5-6 for timing diagram. 5.3.2 reading the conversion data after the mcp3021 acknowledges the address byte, the device will transmit four ? 0 ? bits followed by the upper four data bits of the conversion. the master device will then acknowledge this byte with an ack = low. with the following six clock pulses, the mcp3021 will transmit the lower six data bits from the conversion. the last two bits are ?don?t cares?, and do not contain valid data. the master then sends an ack = high, indicating to the mcp3021 that no more data is requested. the master can then send a stop bit to end the transmission. figure 5-5: executing a conversion. 5.3.3 consecutive conversions for consecutive samples, sampling begins on the fall- ing edge of the last bit of the lower data byte. see figure 5-6 for timing. figure 5-6: continuous conversion. sda s t a r t s t o p a c k t acq + t conv is initiated here address byte address bits device bits 1001 a r / w upper data byte 0000 d d d a c k lower data byte n a k s p 9 8 2 a 1 a 0 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0xx 123456789 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 scl sda f samp = 22.3 ksps (f clk = 400 khz) a c k t acq + t conv is initiated here address byte address bits device bits 1001a2a1a0 r / w upper data byte (n) a c k lower data byte (n) a c k s t acq + t conv is initiated here 0000 d d d 9 87 d 6 d 5 d 4 d 3 d 2 d 1 d 0xx 123456789 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 scl s t a r t 0 28
mcp3021 ds21805b-page 18 ? 2003-2013 microchip technology inc. 6.0 applications information 6.1 driving the analog input the mcp3021 has a single-ended analog input (ain). for proper conversion results, the voltage at the ain pin must be kept between v ss and v dd . if the converter has no offset error, gain error, inl or dnl errors and the voltage level of ain is equal to or less than v ss + 1/2 lsb, the resultant code will be 000h . addi- tionally, if the voltage at ain is equal to or greater than v dd - 1.5 lsb, the output code will be 1ffh . the analog input model is shown in figure 6-1. in this diagram, the source impedance (r ss ) adds to the inter- nal sampling switch (r s ) impedance, directly affecting the time required to charge the capacitor (c sample ). consequently, a larger source impedance increases the offset error, gain error and integral linearity errors of the conversion. ideally, the impedance of the signal source should be near zero. this is achievable with an operational amplifier such as the mcp6022, which has a closed-loop output impedance of tens of ohms. figure 6-1: analog input model, ain. 6.2 connecting to the i 2 c bus the i 2 c bus is an open collector bus, requiring pull-up resistors connected to the sda and scl lines. this configuration is shown in figure 6-2. figure 6-2: pull-up resistors on i 2 c bus. the number of devices connected to the bus is limited only by the maximum bus capacitance of 400 pf. a possible configuration using multiple devices is shown in figure 6-3. figure 6-3: multiple devices on i 2 c bus. c pin v a r ss ain 7pf v t = 0.6v v t = 0.6v i leakage sampling switch ss r s = 1 k ? c sample = dac capacitance v ss v dd = 20 pf 1 na legend v a = signal source r ss = source impedance ain = analog input pad c pin = analog input pin capacitance v t = threshold voltage i leakage = leakage current at the pin due to various junctions ss = sampling switch r s = sampling switch resistor c sample = sample/hold capacitance pic ? sda scl v dd r pu r pu r pu is typically: 10 k ? for f scl = 100 khz 2k ? for f scl = 400 khz mcp3021 analog input signal microcontroller ain sda scl pic16f876 microcontroller mcp3021 10-bit adc tc74 temperature sensor 24lc01 eeprom
? 2003-2013 microchip technology inc. ds21805b-page 19 mcp3021 6.3 device polling in some instances, it may be necessary to test for mcp3021 presence on the i 2 c bus without performing a conversion, described in figure 6-4. here we are set- ting the r/w bit in the address byte to a zero. the mcp3021 will then acknowledge by pulling sda low during the ack clock and then release the bus back to the i 2 c master. a stop or repeated start bit can then be issued from the master and i 2 c communication can continue. figure 6-4: device polling. 6.4 device power and layout considerations 6.4.1 powering the mcp3021 v dd supplies the power to the device as well as the ref- erence voltage. a bypass capacitor value of 0.1 f is recommended. adding a 10 f capacitor in parallel is recommended to attenuate higher frequency noise present in some systems. figure 6-5: powering the mcp3021 . 6.4.2 layout considerations when laying out a printed circuit board for use with analog components, care should be taken to reduce noise wherever possible. a bypass capacitor from v dd to ground should always be used with this device and should be placed as close as possible to the device pin. a bypass capacitor value of 0.1 f is recommended. digital and analog traces should be separated as much as possible on the board, with no traces running underneath the device or the bypass capacitor. extra precautions should be taken to keep traces with high frequency signals (such as clock lines) as far as possible from analog traces. the mcp3021 should be connected entirely to the ana- log ground place, as well as the analog power trace. the pull-up resistors can be placed close to the microcontroller and tied to the digital power or v cc . use of an analog ground plane is recommended in order to keep the ground potential the same for all devices on the board. providing v dd connections to devices in a ?star? configuration can also reduce noise by eliminating current return paths and associated errors (figure 6-6). for more information on layout tips when using the mcp3021 or other adc devices, refer to an688, ?layout tips for 12-bit a/d converter applications? . figure 6-6: v dd traces arranged in a ?star? configuration in order to reduce errors caused by current return paths. 6.4.3 using a reference for supply the mcp3021 uses v dd as power and also as a refer- ence. in some applications, it may be necessary to use a stable reference to achieve the required accuracy. figure 6-7 shows an example using the mcp1541 as a 4.096v 2% reference. figure 6-7: stable power and reference configuration. 123456789 scl sda 1 00 1 a2a1a0 0 ack start bit address byte address bits device bits r/w start bit mcp3021 response v dd v dd a in scl sda to microcontroller 10 f mcp3021 0.1 f v cc r pu r pu v dd connection device 1 device 2 device 3 device 4 v dd v dd 4.096v reference 1f 0.1 f mcp1541 c l a in to microcontroller mcp3021 v cc r pu scl sda
mcp3021 ds21805b-page 20 ? 2003-2013 microchip technology inc. 7.0 packaging information 7.1 package marking information 2 1 3 5 4 5-pin sot-23a (eiaj sc-74) device ???? part number address option sot-23 mcp3021a0t-e/ot 000 gp mcp3021a1t-e/ot 001 gs mcp3021a2t-e/ot 010 gk mcp3021a3t-e/ot 011 gl mcp3021a4t-e/ot 100 gm mcp3021a5t-e/ot 101 gj * mcp3021a6t-e/ot 110 gq mcp3021a7t-e/ot 111 gr * default option. contact microchip factory for other address options. legend: xx...x customer-specific information y year code (last digit of calendar year) yy year code (last 2 digits of calendar year) ww week code (week of january 1 is week ?01?) nnn alphanumeric traceability code pb-free jedec designator for matte tin (sn) * this package is pb-free. the pb-free jedec designator ( ) can be found on the outer packaging for this package. note : in the event the full microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. 3 e 3 e
? 2003-2013 microchip technology inc. ds21805b-page 21 mcp3021 5-lead plastic small outline transistor (ot) (sot23) 10 5 0 10 5 0 ? mold draft angle bottom 10 5 0 10 5 0 ? mold draft angle top 0.50 0.43 0.35 .020 .017 .014 b lead width 0.20 0.15 0.09 .008 .006 .004 c lead thickness 10 5 0 10 5 0 ? foot angle 0.55 0.45 0.35 .022 .018 .014 l foot length 3.10 2.95 2.80 .122 .116 .110 d overall length 1.75 1.63 1.50 .069 .064 .059 e1 molded package width 3.00 2.80 2.60 .118 .110 .102 e overall width 0.15 0.08 0.00 .006 .003 .000 a1 standoff 1.30 1.10 0.90 .051 .043 .035 a2 molded package thickness 1.45 1.18 0.90 .057 .046 .035 a overall height 1.90 .075 p1 outside lead pitch (basic) 0.95 .038 p pitch 5 5 n number of pins max nom min max nom min dimension limits millimeters inches* units 1 p d b n e e1 l c ? ? ? a2 a a1 p1 * controlling parameter notes: dimensions d and e1 do not include mold flash or protrusions. mold flash or protrusions shall not exceed .010? (0.254mm) per side. jedec equivalent: mo-178 drawing no. c04-091 significant characteristic note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging
mcp3021 ds21805b-page 22 ? 2003-2013 microchip technology inc. 8.0 revision history revision b (january 2013) added a note to each package outline drawing.
? 2003-2013 microchip technology inc. ds21805b-page 23 mcp3021 product identification system to order or obtain information, e. g., on pricing or delivery, refer to the factory or the listed sales office . sales and support device: mcp3021t: 10-bit 2-wire serial a/d converter (tape and reel) temperature range: e= -40 ? c to +125 ? c address options: xx a2 a1 a0 a0 = 0 0 0 a1 = 0 0 1 a2 = 0 1 0 a3 = 0 1 1 a4 = 1 0 0 a5 * = 1 0 1 a6 = 1 1 0 a7 = 1 1 1 * default option. contact microchip factory for other address options package: ot = sot-23, 5-lead (tape and reel) part no. x xx address temperature range device examples: a) mcp3021a0t-e/ot: extended, a0 address, tape and reel b) mcp3021a1t-e/ot: extended, a1 address, tape and reel c) mcp3021a2t-e/ot: extended, a2 address, tape and reel d) mcp3021a3t-e/ot: extended, a3 address, tape and reel e) mcp3021a4t-e/ot: extended, a4 address, tape and reel f) mcp3021a5t-e/ot: extended, a5 address, tape and reel g) mcp3021a6t-e/ot: extended, a6 address, tape and reel h) mcp3021a7t-ie/ot: extended, a7 address, tape and reel /xx package options data sheets products supported by a preliminary data sheet may have an errata sheet describing minor operational differences and recommended workarounds. to determine if an errata sheet exists for a particular device, please contact one of the following: 1. your local microchip sales office 2. the microchip worldwide site (www.microchip.com) please specify which device, revision of silicon and data sheet (include literature #) you are using. customer notification system register on our web site (www.microchip.com/cn) to receive the most current information on our products.
mcp3021 ds21805b-page 24 ? 2003-2013 microchip technology inc. notes:
? 2003-2013 microchip technology inc. ds21805b-page 25 information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. it is your responsibility to ensure that your application meets with your specifications. microchip makes no representations or warranties of any kind whether express or implied, written or oral, statutory or otherwise, related to the information, including but not limited to its condition, quality, performance, merchantability or fitness for purpose . microchip disclaims all liability arising from this information and its use. use of microchip devices in life support and/or safety applications is entirely at the buyer?s risk, and the buyer agrees to defend, indemnify and hold harmless microchip from any and all damages, claims, suits, or expenses resulting from such use. no licenses are conveyed, implicitly or otherwise, under any microchip intellectual property rights. trademarks the microchip name and logo, the microchip logo, dspic, flashflex, k ee l oq , k ee l oq logo, mplab, pic, picmicro, picstart, pic 32 logo, rfpic, sst, sst logo, superflash and uni/o are registered trademarks of microchip technology incorporated in the u.s.a. and other countries. filterlab, hampshire, hi-tech c, linear active thermistor, mtp, seeval and the embedded control solutions company are registered trademarks of microchip technology incorporated in the u.s.a. silicon storage technology is a registered trademark of microchip technology inc. in other countries. analog-for-the-digital age, app lication maestro, bodycom, chipkit, chipkit logo, codeguard, dspicdem, dspicdem.net, dspicworks, dsspeak, ecan, economonitor, fansense, hi-tide, in-circuit serial programming, icsp, mindi, miwi, mpasm, mpf, mplab certified logo, mplib, mplink, mtouch, omniscient code generation, picc, picc-18, picdem, picdem.net, pickit, pictail, real ice, rflab, select mode, sqi, serial quad i/o, total endurance, tsharc, uniwindriver, wiperlock, zena and z-scale are trademarks of microchip technology incorporated in the u.s.a. and other countries. sqtp is a service mark of microchip technology incorporated in the u.s.a. gestic and ulpp are registered trademarks of microchip technology germany ii gmbh & co. & kg, a subsidiary of microchip technology inc., in other countries. all other trademarks mentioned herein are property of their respective companies. ? 2003-2013, microchip technology incorporated, printed in the u.s.a., all rights reserved. printed on recycled paper. isbn: 9781620769003 note the following details of the code protection feature on microchip devices: ? microchip products meet the specification cont ained in their particular microchip data sheet. ? microchip believes that its family of products is one of the most secure families of its kind on the market today, when used i n the intended manner and under normal conditions. ? there are dishonest and possibly illegal methods used to breach the code protection feature. all of these methods, to our knowledge, require using the microchip produc ts in a manner outside the operating specif ications contained in microchip?s data sheets. most likely, the person doing so is engaged in theft of intellectual property. ? microchip is willing to work with the customer who is concerned about the integrity of their code. ? neither microchip nor any other semiconduc tor manufacturer can guarantee the security of their code. code protection does not mean that we are guaranteeing the product as ?unbreakable.? code protection is constantly evolving. we at microchip are co mmitted to continuously improvin g the code protection features of our products. attempts to break microchip?s code protection feature may be a violation of the digital millennium copyright act. if such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that act. microchip received iso/ts-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in chandler and tempe, arizona; gresham, oregon and design centers in california and india. the company?s quality system processes and procedures are for its pic ? mcus and dspic ? dscs, k ee l oq ? code hopping devices, serial eeproms, microperipherals, nonvolatile memory and analog products. in addition, microchip?s quality system for the design and manufacture of development systems is iso 9001:2000 certified. quality management s ystem certified by dnv == iso/ts 16949 ==
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